This invention relates to first-in-first-out (FIFO) buffers.
In digital systems, it is sometimes required to transfer data between two asynchronous clock regimes; that is, between first and second groups of logic where the first group is controlled by a first clock signal and the second group is controlled by a second clock signal which is not synchronised with the first clock signal.
In such a system, if no special precautions are taken, there is a possibility that the output data from the first clock regime may change at approximately the same time as it is transferred into the second clock regime. Because of variations in tolerances, the individual bits of a data word transferred in parallel between the first and second clock regimes may come from different clock beats of the first clock regime, resulting in corruption of the data.
A known solution to this problem is to use a FIFO memory to buffer data between the two clock regimes.
One known FIFO memory comprises a plurality of storage locations for storing a plurality of data words. The FIFO is addressed by separate read and write counters, which cause words to be written cyclically into the storage locations and then to be read out in the same cyclic order. However, a problem with this arrangement is that it requires special logic for detecting the buffer full and buffer empty conditions, and for preventing further input or output in these conditions.
The object of the present invention is to provide an improved FIFO buffer for transferring data between two clock regimes, which does not require any such buffer full and buffer empty logic.